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微电子失效分析和纳米材料分析研讨会

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Course Overview

Microelectronic and now Nano-electronic manufacturing has become increasingly challenging with higher density packaging, transistor counts into the billions, dimensional scaling, new materials, and three-dimensional packaging. Yield, reliability, and quality engineering are increasingly critical to quick and cost-effective product introduction and client satisfaction. Finding, understanding, and correcting defects are all critical to improving yield, reliability, and quality. Numerous defect mechanisms can cause failure and a large number of complicated techniques is required to localize, identify, and characterize them.
This course provides an overview of microelectronic test, electrical faults and failures, physical defects, fault isolation, and failure analysis techniques for simple and advanced ICs and microelectronic packages. The theory and application of testing, characterization, and analytical tools, techniques, and instruments will be covered along with a wide variety of defect types and examples.
This course will also provide an overview and introduce applications of surface analysis techniques (such as AES, XPS, FTIR, D-SIMS, TOF-SIMS, AFM, EBSD etc.) and physical analysis techniques (such as SEM, EDX, FIB and TEM).
 
Course Objective
This course will provide attendees with a broad overview of defects, test, diagnosis, failure analysis, and Nano-materials characterization as well as the relevant theory and application of numerous analytical techniques and methods. Upon completion, attendees will be able to understand the latest advanced material analysis techniques/tools, as well as the basic operating principles, use, and limitations of all common methods for analyzing manufacturing yield, reliability, and quality failures.
 
Who Should Attend?
 This course is designed for test and debug personnel, failure analysts, and characterization, yield, and reliability analysis engineers, technicians, managers, and anyone who submits devices to, performs, or analyzes results from failure analysis laboratories of semiconductor, wafer fabrication, assembly houses, LED/LCD and Nano-materials etc. Researchers, developers, managers of material analysis laboratory/university/institute/manufacturing, and vendors of fault isolation and related equipment and failure analysis tooling in general can also benefit.
 
 
Course Outline
 
Day 1 (Morning Session) Mr. David Vallett
    1. Microelectronic failures, faults, and defects
    2. Basic IC test approaches
    3. Overview of scan-chain diagnostics
    4. Failure types
    5. Fault models
    6. Manufacturing defect mechanisms, morphology, and root cause
    7. Reliability defect mechanisms and morphology, and root cause
 
Day 1 (Afternoon Session) Mr. David Vallett
a.       Introduction to failure analysis (FA)
b.      The role of FA in semiconductor development and manufacturing
c.       Failure analysis approaches for yield, reliability qualifications, and client returns
d.      Characterization and preparation for failure analysis
e.       The importance of fault isolation
f.       Electrical fault isolation principles and techniques (e.g. nanoprobing, time-domain reflectometry, diagnostic testing)
g.      Physical fault isolation principles and techniques (e.g., electron, ion, magnetic, photon emission, thermal imaging, and laser scanning microscopy)
 
Day 2 (Morning Session)  Mr. David Vallett
a.       Physical failure analysis
b.      Wet chemical and plasma etching
c.       Mechanical delayering
d.      Focused ion beam (FIB) deprocessing 
e.       Ion milling
f.       Acoustic microscopy
g.      Optical microscopy
h.      Scanned probe / atomic force microscopy
i.        Electron and ion beam microscopy
j.        X-ray microscopy and tomography 
k.      Chemical and materials surface and bulk microanalysis
l.        Emerging challenges of 3D packaging failure analysis
m.    Semiconductor technology challenges in failure analysis
n.      Q&A Session
 
Day 2 (Afternoon Session) Dr. Hua Younan
a.       Introduction to surface failure analysis
b.      Energy-dispersive X-ray microanalysis
c.       Auger Electron Spectroscopy
d.      X-ray Photoelectron Spectroscopy
e.       Fourier Transform Infrared Spectroscopy
f.       Dynamic Secondary Ion Mass Spectroscopy
g.      Time of Flight Secondary Ion Mass Spectrometry
h.      Atomic Force Microscope
i.        Electron Backscattered Diffraction
j.        Case-study
 
Day 3 (Morning Session)  Dr. Chen Yixin
a.       Dual Beam FIB-SEM system
b.      Ion Milling
c.       FIB-TEM Sample Preparation
d.      Advanced HR-TEM Characterization
e.       Case-study
 
 
Instructor - Mr. David Vallett
 
 
 Mr. David Vallett is a Failure Analysis manager in the Worldwide Analytical Services Technology Quality organization with IBM Systems & Technology Group in Burlington, VT, USA. He has over 30 years experience in CMOS characterization and failure analysis and holds the BS degree in electrical engineering from the University at Buffalo, New York, USA. He presently manages a department responsible for technology qualification failure analysis, fault isolation, and advanced packaging failure analysis having capabilities in all facets of IC physical failure analysis, electrical and physical fault isolation, depackaging and silicon micromachining, nanoprobing, and X-ray tomography. Mr. Vallett is widely published in the field with five best-paper awards and has given a number of lectures on analytical technology challenges in both micro and nanoelectronics. He holds fifteen US patents and shared in IBM's Outstanding Technical Achievement award for his contributions to picosecond imaging circuit analysis (PICA) using time-resolved photon emission microscopy. He is a senior member of the IEEE, a member of the Electronic Device
 Failure Analysis Society board of directors, and belongs to Tau Beta Pi - the National Engineering Honor Society. He is a past chair of the International SEMATECH Product Analysis Forum and was selected as the 2008 General Chair for ISTFA - the International Symposium for Testing and Failure Analysis.
 
PROFESSIONAL ACTIVITIES:
·         International Symposium for Testing and Failure Analysis (ISTFA) – General Chair 2008
·         IEEE International Reliability Physics Symposium (IRPS), Failure analysis session chair
·         International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) -
committee member
·         International SEMATECH, Product Analysis Forum (PAF) member and chair (1997, 2004
·         Senior Member IEEE
·         EDFAS (Electronic Device Failure Analysis Society) Board of Directors member
·         Tau Beta Pi - National Engineering Honor Society
 
AWARDS
·         Seventeen US patents
·         IBM 7th level Patent Plateau
·         IBM Outstanding Technical Achievement award for Picosecond Imaging Circuit Analysis (PICA)
·         International Test Conference (ITC), Best Paper Award, 1999
·         International Symposium for Testing and Failure Analysis (ISTFA), Best Paper Award 1985, 2002
·         ISTFA, Outstanding Paper Award, 1998
 
 
 
 
 
 
 
Instructor – Dr. Hua Younan
 
 
 Dr. Hua Younan received his Ph. D degree in Physics from National University of Singapore in 1994. He currently serves as a Senior Director in WinTech Nano-Technology Service Pte Ltd, Singapore, which is a worldwide analytical services company. He takes full responsibility of the laboratory’s daily business operation and the company’s technical development. Dr Hua's professional background includes services in both technical and management positions. From 1995 to 2013, he served at GLOBALFOUNDRIES, Singapore (formerly Chartered Semiconductor) as a director of failure analysis laboratory. With corporate and research experience (such as SEM/EDX, TEM, FIB, SIMS, Auger, XPS, FTIR, XRD, 4-PB, VPD, ICP-MS, GC-MS, IC, etc.), he and his FA teams supported 6 wafer Fabs (8” & 12”) in Singapore in their developments, productions & customer service.
 Before joining Chartered Semiconductor/GLOBALFOUNDRIES, Dr Hua served at the National University of Singapore and Nanjing Institute for 13 years. In total, he has more than 30 years of working experience in material science & engineering research, failure analysis for semiconductor & wafer fabrication.
 Since 1982, he has published more than 260 technical papers and filed 3 patents & 5 company trade secrets. Dr Hua has conducted deep theoretical studies in areas such as failure analysis techniques in wafer fabrication, microchip Al bondpad corrosion & eliminating solutions, chemical deprocessing techniques & elimination of Silicon crystalline defects, energy-dispersive X-ray microanalysis, X-ray fluorescence analysis and surface analysis techniques such as AES, XPS and SIMS.
 
PROFESSIONAL ACTIVITIES:
·         International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) - Committee member (2012, 2014)
·         SIMS IV China/ISSIMS Beijing 2008 – Scientific committee member
·         International Symposium for Testing and Failure Analysis (ISTFA/USA) – Section Chair/Paper contributor (1997-2014)
·         Invited Scientific/Technical Talks:
·         Applications of SEM, EDX, Auger, XPS and SIMS Techniques in Failure Analysis of Wafer Fab - PSB (Singapore Product & Standard Board), Singapore (2001)
·         Contamination Analysis on Microchip Al Bondpads by Auger, XPS and TOF-SIMS Techniques - A-Star (新加坡科技研究院)- IME and SSAIG, Singapore (2002).
·         Theoretical Studies & Explanations of Fluorine-Induced Corrosion on Microchip Al Bondpads - A-Star-IME and SSAIG, Singapore (2003).
·         Studies on Fluorine Contamination and Corrosion in Wafer Fab - A-Star-DSI & IEEE, Singapore (2005).
·         Failure Analysis of Fluorine Contamination and Corrosion in Semiconductor and Wafer Fab - Tsinghua University (清华大学), Beijing (2005).
·         A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication - A-Star-DSI, Singapore (2009).
·         Studies and Applications of Surface Analysis Techniques in Wafer Fabrication - A-Star-IMRE, Singapore (2010)
·         Failure Analysis of Vt Shift and GOI Related Failures in Wafer Fabrication using Combined FA Techniques - A-Star-DSI, Singapore (2010).
 
AWARDS
·         Three US patents (filed) and two China patents (in process)
·         International Symposium for Testing and Failure Analysis (ISTFA), Best Paper Award (Session), 2002
 
Instructor – Dr. Chen Yixin
 
 
 Dr. Chen Yixin obtained her DPhil degree in Materials Science from University of Oxford in 2010. She was supervised by Professor David Cockayne (Fellow of the Royal Society, former president of International Federation of Societies for Electron Microscopy) during her DPhil study. Currently, she serves as an Assistant Director in WinTech Nano-Technology Service Pte Ltd.
 In close collaboration with Samsung, she has made significant contributions in developing the new generation of semiconductor memory materials. Having 10 years’ experience in electron microscopies and related techniques, she is highly skilled in characterizing various types of materials including semiconducting materials, alloys, ceramics, carbon based materials, etc. Moreover, she has demonstrated strong capabilities in developing novel techniques and solving complicated materials and failures problems.
 
PROFESSIONAL ACTIVITIES:
  • International Symposium for Testing and Failure Analysis (ISTFA/USA) – Paper contributor (2014)
  • International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) - Paper contributor (2012, 2014)
  • Invited speaker, Singapore FIB/TEM User Group Meeting, Singapore, 2011
  • Invited speaker, Electron Microscopy Group, INT, KIT, Karlsruhe, Germany, 2011
  • Invited speaker, Faculty of Physics, University of Vienna, Vienna, Austria, 2011
  • Oral presentation, 12th CMA-UK Conference, Oxford, UK, 2008
  • Oral presentation, GLAMOR workshop, Cambridge, UK, 2007
  • Poster presentation, E*PCOS Conference, Grenoble, France, 2006

     

 

 

 

 
AWARDS
·         Overseas Research Scholarship (ORS), awarded by the UK Government.
·         Linacre Materials Scholarship, awarded by Linacre College, Oxford.

 

                                            微电子失效分析和纳米材料分析研讨会

 

 

(Microelectronic Failure Analysis and Nano-Materials Characterization)
 
胜科纳米(苏州)有限公司将在今年12月分别在上海和苏州举办两场微电子失效分析和纳米材料分析研讨会,我们热忱地邀请您们参加。
 
来自美国著名大型半导体公司IBM的David Vallett先生将邀请为主讲老师。David Vallett先生是一位国际著名的微电子失效分析专家,拥有30多年的微电子失效分析和半导体材料分析的工作经验,在微电子失效分析的学术领域有很厚的学术造诣。他曾受邀在美国和新加坡等地作过多次专题学术演讲和授课。这将是他第一次受邀在国内作演讲和授课,希望各位领导,专家和同仁尽快报名,以免向隅。
 
胜科纳米公司是一家提供高端失效分析和材料分析服务的内资公司,拥有一批具有国际著名半导体公司和名牌大学背景的强大专家团队。在即将举办的微电子失效分析和纳米材料分析研讨会上,来自胜科纳米(新加坡)的两位专家华佑南博士和陈以欣博士也将就材料表面和物理分析专题进行学术演讲与最新案例研讨。华佑南博士曾在新加坡淡马锡属下的特许半导体制造公司和国际大型半导体制造公司格罗方德从事多年的微电子失效分析和材料分析的研究,期间著有大量学术论文和专利,在相关领域有极深厚的学术造诣。陈以欣博士则曾在英国牛津大学深造和工作多年,期间著有大量学术论文,特别是在透射电镜分析应用,材料晶体学以及半导体工艺及器件失效分析等方面进行过深入研究。
 
 研讨会安排:
·         时间                 2.5
·         日期                 : 2014 12 8-10
·         地点                : 上海/苏州 (详细地点另行通知)
·         收费                 : 6000人民币/每人
 
 

 

 

请报名的单位或个人在10月25日前将附件注册表发到huangcj@szicc.com.cn 
(如果在10月1日前注册将享有优惠:注册3人可另加一人免费。)

 

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